A method for forming a related MIM (metal insulator metal) capacitor of a semiconductor device will be described with reference to FIG. 1. First, a typical semiconductor logic process is performed on a semiconductor substrate, such as a silicon substrate, and an interlayer dielectric layer is formed on the semiconductor substrate. Then, a lower metal layer 10 is formed on the interlayer dielectric layer and an insulating layer 12 is deposited on the lower metal layer 10. The insulating layer 12 can be formed in a single layer structure or a multi-layer structure by using SiN, SiH4, or SiON. Next, an upper metal layer 14 including TiN is deposited on the insulating layer.
A photoresist pattern for patterning an upper electrode of the MIM capacitor is formed on the upper metal layer 14. After that, the upper metal layer 14 is etched by performing a plasma etching process using Cl-based gas, thereby forming the upper electrode of the capacitor. Then, an insulating layer formed below the upper electrode is etched by performing a plasma etching process using F-based gas.
As the etching processes have been finished, the pattern is removed and a process for depositing an interlayer dielectric layer including IMD (inter metal dielectric) material is performed. However, the method for forming the related MIM capacitor represents disadvantages in terms of TDDB (time dependent dielectric breakdown). During the MIM etching process for forming the MIM capacitor, an end part of an MIM layer is formed with a relatively thin thickness, so that the electric field is concentrated on the end part of the MIM layer. Thus, when the TDDB test is performed, the end part of the MIM layer may be melted, thereby causing disconnection between metals.